FFT Accelerator
6-6 ADSP-214xx SHARC Processor Hardware Reference
Data Memory
The accelerator has a 1024 location deep, 32-bit wide data memory, orga-
nized into four independent blocks. Blocks are grouped in sets of two that
are used to fetch or store real and imaginary parts of data simultaneously.
Fetches and stores are accomplished by ping-ponging the read and write
buffers.
Coefficient Memory
The accelerator has a 512 location deep, 32-bit wide twiddle memory,
organized into two independent blocks (256x2). It allows fetching real
and imaginary twiddles simultaneously.
Accelerator States
The FFT accelerator has five different states:
1. Reset
2. Idle
3. Reading
4. Processing
5. Writing
These states are described in detail in the following sections.
Reset State
Reset mode is activated either by setting the FFT_RST bit in the FFTCTL1
register or by applying logic low to the RESET input pin.
If reset is activated by setting the
FFT_RST bit, this bit must be cleared to
bring the accelerator out of reset.
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