ADSP-214xx SHARC Processor Hardware Reference 14-9
Precision Clock Generator
The phase shift between clock and frame sync outputs may be pro-
grammed using the
PCG_PW and PCG_CTLxx registers under these
conditions:
• The input clock source for the clock generator output and the
frame sync generator output is the same.
• The clock and frame sync are enabled at the same time using a sin-
gle atomic instruction.
• The frame sync divisor is an integral multiple of the clock divisor.
When using a clock and frame sync as a synchronous pair, the units
must be enabled in a single atomic instruction before their parame-
ters are modified. Both units must also be disabled in a single
atomic instruction as shown below.
r0 = CLKDIV_A|PHASE_LO_A;
dm(PCG_CTLA1) = r0;
r0 = FSDIV_A|PHASE_HI_A|ENCLKA|ENFSA;
/* program dividers and enable CLK and FS */
dm(PCG_CTLA0) = r0;
If the phase shift is zero (see Figure 14-2), the clock and frame sync out-
puts rise at the same time. If the phase shift is one, the frame sync output
transitions one input clock period ahead of the clock transition. If the
phase shift is divisor – 1, the frame sync transitions divisor – 1 input clock
periods ahead of the clock transitions
Pulse Width
Pulse width is the number of input clock periods for which the frame sync
output is high.
A 16-bit value determines the width of the framing pulse. Settings for
pulse width can range from zero to
DIV – 1. The pulse width should be less
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