Effect Latency
15-28 ADSP-214xx SHARC Processor Hardware Reference
from
RXSPI, but their contents are identical to that of RXSPI. When RXSPI
is read from core, the RXS bit is cleared (read only-to-clear) and an SPI
transfer may be initiated (if TIMOD = 00). No such hardware action occurs
when the shadow register is read. RXSPI_SHADOW is only accessible by the
core.
Internal Loopback Mode
In this mode different types of loopback are possible since there is only
one DMA channel available:
• Core receive and transmit transfers
• Transmit DMA and core receive transfers
• Core Transmit and DMA receive transfers
To loop data back from MOSI to MISO, the MISO pin is internally discon-
nected. The MOSI pin will contain the value being looped back. Programs
should set the SPIEN, SPIMS, and ILPBK bits in the SPICTLx register.
Loopback operation is only used in master mode.
Loop Back Routing
The SPI supports an internal loop back mode using the SRU. For more
information, see “Loop Back Routing” on page 9-40.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
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