Clocking
10-8 ADSP-214xx SHARC Processor Hardware Reference
operation mode, refer to Table 10-7 on page 10-24 and “Operation
Modes” on page 10-21.
Serial Port Error Registers (SPERRxx). Two error registers (
SPER-
RCTLx
/SPERRSTAT) are used to observe and control error handling during
transfers. Detected errors can be frame sync violation or buffer
over/underflow conditions. For more information, see “Error Detection”
on page 10-51 and “Error Status” on page 10-53.
Multichannel Control Registers (SPMCTLx). There is one global control
and status register for each SPORT (SPORT7–0) for multichannel opera-
tion. These registers define the number of channels, provide the status of
the current channel, enable multichannel operation, and set the multi-
channel frame delay.
Master Clock Divider Registers (DIVx). The DIVx registers contain divi-
sor values that determine frequencies for internally-generated clocks and
frame syncs. If your system requires more precision and less noise and jit-
ter, refer to Chapter 14, Precision Clock Generator.
Clocking
The fundamental timing clock of the SPORT modules is peripheral
clock/4 (PCLK/4). Each serial port has a clock signal (SPORTx_CLK) for
transmitting and receiving data on the two associated data signals. The
clock signals are configured by the
ICLK and CKRE bits of the SPCTLx con-
trol registers. A single clock signal clocks both A and B data signals (either
configured as inputs or outputs) to receive or transmit data at the same
rate.
Master Clock
The CLKDIV bit field specifies how many times the processor’s internal
clock (
PCLK) is divided to generate the transmit and receive clocks. The
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