Programming Models
3-122 ADSP-214xx SHARC Processor Hardware Reference
4. If scatter/gather DMA is desired, program additional writes to the
TCEP and TPEP registers.
5. Enable DMA using the DMAEN bit, and set the transfer direction
using the TRAN bit in the DMACx registers. If scatter/gather DMA is
desired, set the TLEN bit. It is advised that the DMA FIFOs are
flushed using the DFLSH bit when DMA is enabled.
Once the DMA control register is initialized, the DMA engine fetches the
DMA descriptors from the address pointed to by CPEP. Once the DMA
descriptors are fetched then the DMA (or the tap list DMA) process starts.
Once the DMA (or tap list DMA) is complete, the new DMA descriptors
are loaded and the process is repeated until CPEP = 0x0. A DMA comple-
tion interrupt is generated at the end of each DMA block or at the end of
entire chained DMA, depending on the PCI bit setting.
Chained DMA
Use the following procedure to set up and run a chained DMA on the
external port.
1. Clear the chain pointer register.
2. Configure the AMICTLx registers to enable the AMI, set the desired
wait states, the data bus width, and so on. Configure the SDCTL reg-
ister to enable the SDRAM/DDR2, configure the desired clock and
timing settings, data bus width, and other parameters.
3. Initialize the
CPEP register and set the PCI bit if interrupts are
required after the end of each DMA block. Set the CPDR bit if dif-
ferent DMA direction is required in conjunction with the OFCEN bit
in the
DMACx register.
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