ADSP-214xx SHARC Processor Hardware Reference 21-5
Two Wire Interface Controller
Register Overview
This section provides brief descriptions of the major registers. For com-
plete information see “Two Wire Interface Registers” on page A-253.
Slave Mode Control Register (TWISCTL). Controls the logic associated
with slave mode operation. Settings in this register do not affect master
mode operation and should not be modified to control master mode
functionality.
Slave Mode Status Register (TWISSTAT). During and at the conclusion
of slave mode transfers, the TWISSTAT holds information on the current
transfer. Generally, slave mode status bits are not associated with the gen-
eration of interrupts. Master mode operation does not affect slave mode
status bits.
Master Mode Control Register (TWIMCTL). Controls the logic associ-
ated with master mode operation. Bits in this register do not affect slave
mode operation and should not be modified to control slave mode
functionality.
Master Mode Status Register (TWIMSTAT). Holds information during
master mode transfers and at their conclusion. Generally, master mode
status bits are not directly associated with the generation of interrupts but
offer information on the current transfer. Slave mode operation does not
affect master mode status bits.
Control Timer Register (TWIMITR). Enables the TWI module and
establishes a relationship between the peripheral clock (
PCLK) and the TWI
controller’s internally-timed events. The internal time reference is derived
from PCLK using the prescaled value shown below.
PRESCALE = f
PCLK
/10 MHz
Serial Clock Divider Register (TWIDIV). During master mode opera-
tion, the TWIDIV register values are used to create the high and low
durations of the
TWI_CLOCK.
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