ADSP-214xx SHARC Processor Hardware Reference I-3
Index
booting (continued)
SPI slave mode, 23-15
buffer
addressing, 2-25
data, 2-10
DMA use in, 2-24
SPORT data, 10-1
TCB allocation, 2-33
buffer, pin, 9-7
buffer hang disable (BHD) bit, 10-54,
A-156, A-160, A-165
buses
errors in, 3-44, 3-80
external bus data width (BW) bit, A-22,
A-48
external port, 2-43
hold cycle bit, A-22, A-49
I
2
S and, C-3
idle cycle bit, A-23, A-50
I/O address (IOA), 2-25
IO data (IOD), 2-30
I/O processor (IOP), 10-47
peripheral, 2-44
bypass as a one-shot (strobe pulse), 14-13
C
capacitors
bypass, 23-36
decoupling, 23-36
CAS latency
bit (SDCL), A-53
cautions and warnings
DMA transfers, 2-28
I/O processor, 2-28
SPORTs, 10-42
center-aligned paired PWM
double-update mode, 7-10
single-update mode, 7-9
chain assignment, I/O processor, 2-33
chained DMA, 2-23, 2-29, 2-32, 2-34
chained DMA enable (SCHEN_A and
SCHEN_B) bit, A-156, A-160
chained DMA sequences, 2-11
chain pointer (CPSPI) registers, SPI,
15-32
chain pointer (CPSPx) registers,
SPORTs, 2-12, 10-47
chain pointer (CPx) registers, 2-33
chain pointer registers (general), 2-11
enable (SCHEN_A and SCHEN_B) bit,
10-47, A-164
FFT accelerator, 2-18
FIR accelerator, 2-16
IIR accelerator, 2-17
link port, 2-15
SPI, 2-14
SPORTs, 2-14, 10-47, A-156, A-160,
A-164
UART, 2-15, 20-14
chaining enable bit (CHEN), 2-34
chain insertion mode, SPORT, 10-48
chain pointer registers, 2-7, 2-11
changing SPI configuration, 15-29
channel
allocation for DMA, 2-3
arbitration, fixed/floating, 2-43
defined, 2-2
DMA, 2-23
granting access, 2-31
interrupt, 2-45,
2-48
pr
iority, 2-31
priority for DMA, 2-30
registers, listed, 2-36
channel B transmit status register
(SPDIF_TX_CHSTB), A-203, A-204
channel selection registers, 10-36
clearing interrupts, latches, B-3
CLKOUTEN (clockout enable) bit, A-11,
A-16
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