ADSP-214xx SHARC Processor Hardware Reference A-165
Registers Reference
20 SDEN_B Enable Channel B Serial Port DMA.
0 = Disable serial port channel B DMA
1 = Enable serial port channel B DMA
21 SCHEN_B Enable Channel B Serial Port DMA Chaining.
0 = Disable serial port channel B DMA chaining
1 = Enable serial port channel B DMA chaining
22 Reserved
23 BHD Buffer Hang Disable.
0 = Indicates a core stall. The core stalls when it tries to write to a full
transmit buffer or read an empty receive buffer FIFO.
1 = Ignore a core hang
24 Reserved
25 SPTRAN Data Direction Control. This bit controls the data direction of the
serial port channel A and B signals.
When cleared (= 0) the SPORT is configured to receive on both chan-
nels A and B. When configured to receive, the RXSPxA and RXSPxB
buffers are activated, while the receive shift registers are controlled by
SPORTx_CLK and SPORTx_FS. The TXSPxA and TXSPxB buffers
are inactive.
When set (= 1) the SPORT is configured to transmit on both chan-
nels A and B. When configured to transmit, the TXSPxA and
TXSPxB buffers are activated, while the transmit shift registers are
controlled by SPORTx_CLK and SPORTx_FS. The RXSPxA and
RXSPxB buffers are inactive.
Table A-86. SPCTLx Register Bit Descriptions (Packed and Multichannel)
(RW) (Cont’d)
Bit Name Description
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