ADSP-214xx SHARC Processor Hardware Reference 4-7
Link Ports—ADSP-2146x
5. Receiver accepts the remaining word even if
LACK is deasserted. The
transmitter does not send the following word.
6. Transmit data for next word is held until LACK is asserted.
The receive buffer may fill if a higher priority DMA, core I/O processor
register access, or chain loading operation is occurring. The LACKx signal
may deassert when it anticipates the buffer may fill. The LACKx signal is
reasserted by the receiver as soon as the internal DMA grant signal has
occurred, freeing a buffer location or the core reads the receive buffer
RXLBx thereby freeing a buffer location. The LACKx signal inhibits trans-
mission of next word and not of the current byte.
Data is latched in the receive buffer on the falling edge of LCLKx.
The receive operation is purely asynchronous and can occur at any
frequency up to 166 MHz or peripheral clock frequency (which-
ever is less).
When a link port is not enabled, LDAT7-0, LCLKx and LACKx are
three-stated. When a link port is enabled to transmit, the data pins are
driven with whatever data is in the output buffer, LCLKx is driven high and
LACKx is three-stated. When a port is enabled to receive, the data pins and
LCLKx are three-stated and LACKx is driven high.
Intercommunication
The transmitter and the receiver may be enabled at different times. The
LACKx and LCLKx signals should be held low with the external pull-down
resistors. If the transmitter is enabled before the receiver, the
LACKx signal
(of the receiver) is held low and transmission is held off. If the receiver is
enabled before the transmitter, the
LCLKx signal (of the transmitter) is held
low by the pull-down and the receiver is held off.
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