Functional Description
10-12 ADSP-214xx SHARC Processor Hardware Reference
Figure 10-2 shows a block diagram of a serial port. Setting the
SPTRAN bit
enables the data buffer path, which, once activated, responds by shifting
data in response to a frame sync at the rate of SPORTx_CLK. An application
program must use the correct serial port data buffers, according to the
value of SPTRAN bit. The SPTRAN bit enables either the transmit data buffers
for the transmission of A and B channel data, or it enables the receive data
buffers for the reception of A and B channel data. Inactive data buffers are
not used.
The processor’s SPORTs are not UARTs and cannot communicate with
an RS-232 device or any other asynchronous communications protocol.
One way to implement RS-232 compatible communication with the pro-
cessor is to use two of the FLAG pins as asynchronous data receive and
transmit signals.
Data Types and Companding
Linear transfers occur in the primary channel, if the channel is active and
companding is not selected for that channel. Companded transfers occur
if the channel is active and companding is selected for that channel. The
multichannel compand select registers, MTxCCSy and MRxCCSy, specify the
transmit and receive channels that are companded when multichannel
mode is enabled.
Transmit or receive sign extension is selected by bit 0 of
DTYPE in the
SPCTLx register and is common to all transmit or receive channels. If bit 0
of DTYPE is set, sign extension occurs on selected channels that do not have
companding selected. If this bit is not set, the word contains zeros in the
MSB positions. Companding is not supported for B channel. For B
channels, transmit or receive sign extension is selected by bit 0 of DTYPE in
the
SPCTLx register.
The compression for transmission requires a minimum word
length of 8 (SLEN = 8) for proper function. If SLEN < 8 the expan-
sion may not work correctly.
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