Operating Modes
15-14 ADSP-214xx SHARC Processor Hardware Reference
SPI Modes
The SPI supports four different combinations of serial clock phases and
polarity called SPI modes. The application code can select any of these
combinations using the CLKPL and CPHASE bits (10 and 11).
Figure 15-5 on page 15-15 shows the transfer format when
CPHASE = 0 and
Figure 15-6 on page 15-16 shows the transfer format when
CPHASE = 1.
Each diagram shows two waveforms for SPICLK—one for CLKPL = 0 and
the other for CLKPL = 1. The diagrams may be interpreted as master or
slave timing diagrams since the SPICLK, MISO, and MOSI pins are directly
connected between the master and the slave. The MISO signal is the output
from the slave (slave transmission), and the MOSI signal is the output from
the master (master transmission).
The SPICLK signal is generated by the master, and the SPIDS signal repre-
sents the slave device select input to the processor from the SPI master.
The diagrams represent 8-bit transfers (WL = 0) with MSB first (MSBF = 1).
Any combination of the WL and MSBF bits of the SPICTL register is allowed.
For example, a 16-bit transfer with the LSB first is one possible
configuration.
The clock polarity and the clock phase should be identical for the master
device and slave devices involved in the communication link. The transfer
format from the master may be changed between transfers to adjust to var-
ious requirements of a slave device.
When CPHASE = 0, the slave-select line, SPIDS, must be inactive
(
HIGH) between each word in the transfer. Even in SPI slave mode
when
CPHASE = 0, the master should de assert the SPIDS line
between each transfer. When CPHASE = 1, SPIDS may either remain
active (
LOW) between successive transfers or be inactive (HIGH).
Figure 15-5 shows the SPI transfer protocol for
CPHASE = 0. Note that
SPICLK starts toggling in the middle of the data transfer where the bit set-
tings are
WL = 0, and MSBF = 1.
To Next Page
Loading...
Need help?
General
