Index
I-12 ADSP-214xx SHARC Processor Hardware Reference
G
generators, optional reset, 23-42
GM (get more data) bit, A-233
ground plane, in PCB design, 23-37
group descriptions, signal routing unit,
9-17
H
handshake, DMA, 2-30
hardware reset, 23-3
hold cycle (external bus) bit, A-22, A-49
hold time
inputs, 23-36
recognition of asynchronous input,
23-36
hysteresis on RESET
pin, 23-34
I
I
2
C port. See TWI controller
I
2
S
(Tx/Rx on left channel first), 10-24
ICLK (internal clock select) bit, A-154,
A-159, A-163
idle cycle (external bus) bit, A-23, A-50
IDP
address, DMA, 11-20
address, ping-pong DMA, 11-21
buffer, 2-10
channel 0 diagram, 11-9
control (IDP_CTL0) register, 11-29,
A-175
control (IDP_CTL1) register, 11-28,
A-177, A-178
(DAI) interrupt service routine
steps, 11-23
DMA control registers, A-174
DMA count (IDP_DMA_Cx) register,
11-20, 11-21
IDP (continued)
DMA index (IDP_DMA_Ix) register,
11-20, 11-21
DMA modify (IDP_DMA_Mx) register,
11-20, 11-21
FIFO (IDP_FIFO) register, 11-14,
11-15, 11-23
FIFO memory data transfer, 11-14
FIFO register (IDP_FIFO register),
11-14
illustrated, 11-2
interrupt driven transfers, 11-15
interrupts, 11-15, 11-27
memory data transfer, 11-14
packing modes, 11-10, 11-13
PDAP control (IDP_PDAP_CTL)
register, A-179
PDAP control (IDP_PP_CTL) register,
A-179
ping-pong DMA, 11-21
polarity of left-right encoding, 11-18
serial inputs, 11-6
IDP bits
bus hang disable (IDP_BHD), 11-25,
A-176
clear buffer overflow (IDP_CLROVR),
A-176
DMA enable (IDP_DMA_EN), 11-29,
A-176
DMA status (IDP_DMAx_STAT),
11-22, A-183
enable (IDP_ENABLE), 11
-29, 11-30,
A-176
FIFO number of samples
(IDP_FIFOSZ), A-183
FIFO samples exceed interrupt
(IDP_FIFO_GTN_INT), 11-27
frame sync format (IDP_SMODEx),
11-15, 11-17, 11-27, A-177
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