ADSP-214xx SHARC Processor Hardware Reference A-163
Registers Reference
Table A-86. SPCTLx Register Bit Descriptions (Packed and Multichannel)
(RW)
Bit Name Description
0 Reserved
2–1 DTYPE Data Type Select. Selects the data type formatting for multichan-
nel/packed mode transmissions. For multichannel/packed mode A
channels, selection of companding mode and MSB format are inclu-
sive:
Serial Data Channel A Type Formatting
x0 = Right-justify, zero-fill unused MSBs
x1 = Right-justify, sign-extend unused MSBs
1x = Compand using μ-law
1x = Compand using A-law
For multichannel/packed mode B channels, companding mode not
available.
Serial Data Channel B Type Formatting
0 = Right-justify, zero-fill unused MSBs
1 = Right-justify, sign-extend unused MSBs
The transmit buffer does not zero-fill or sign-extend transmit
data words; this only takes place for the receive buffer.
3LSBF Serial Word Endian Select.
0 = Big endian (MSB first)
1 = Little endian (LSB first)
8–4 SLEN Serial Word Length Select. Selects the word length in bits. Word sizes
can be from 3 bits to 32 bits.
9PACK 16-bit to 32-bit Word Packing Enable.
0 = Disable 16- to 32-bit word packing
1 = Enable 16- to 32-bit word packing
10 ICLK Internal Clock Select. Select the SPORT clock.
0 = Select external clock
1 = Select internal clock
11 OPMODE Sport Operation Mode.
0 = Multichannel mode
1 = Packed mode
Note for multichannel operation, the SPMCTLx registers must be
programmed.
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