ADSP-214xx SHARC Processor Hardware Reference 2-19
I/O Processor
External Port TCB
The external port interface supports many different types of DMA, result-
ing in different lengths of TCBs. The TCB size varies from six locations
(chained DMA) to 13 locations (delay line DMA). Table 2-22 shows the
required TCBs for chained DMA.
The order the descriptors are fetched with circular buffering enabled is
shown in Table 2-23.
Table 2-22. External Port TCBs
Address Register
CP[18:0] CPEP
CP[18:0] + 0x1 EMEP
CP[18:0] + 0x2 EIEP
CP[18:0] + 0x3 ICEP
CP[18:0] + 0x4 IMEP
CP[18:0] + 0x5 IIEP
Table 2-23. External Port TCBs for Circular DMA
Address Register
CP[18:0] CPEP
CP[18:0] + 0x1 ELEP
CP[18:0] + 0x2 EBEP
CP[18:0] + 0x3 EMEP
CP[18:0] + 0x4 EIEP
CP[18:0] + 0x5 ICEP
CP[18:0] + 0x6 IMEP
CP[18:0] + 0x7 IIEP
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