SDRAM Controller (ADSP-2147x/ADSP-2148x)
3-34 ADSP-214xx SHARC Processor Hardware Reference
•t
REF
= 64 ms
• NRA = 8192 row addresses
•t
RAS
= 6
•t
RP
= 3
This means RDIV is 0x406 (hex) and the SDRAM refresh rate control reg-
ister is written with 0x406.
The RDIV value must be programmed to a nonzero value if the SDRAM
controller is enabled. When RDIV = 0, operation of the SDRAM controller
is not supported and can produce undesirable behavior. Values for RDIV
can range from 0x001 to 0xFFF.
Notice that some SDRAM vendors use separate timing specifica-
tions for the row active time (t
RC
) and row refresh time (t
RFC
).
The controller does ignore the t
RFC
spec. For auto-refresh, it use
the equation t
RC
= t
RAS
+ t
RP
. However since both timing specifi-
cations must meet (especially for extended temperature range) the
modification of t
RAS
specification resolves the timing equation
without performance degradation (t
RFC
= t
RAS
+ t
RP
).
Internal SDRAM Bank Access
The following sections describe the different scenarios for SDRAM bank
access.
Single Bank Access
The SDC keeps only one page open at a time if all subsequent accesses are
to the same row or another row in the same bank.
RDIV
133 10
6
()64×× 10
3–
()×
8192
-------------------------------------------------------------------
63+() 1030=–=
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