ADSP-214xx SHARC Processor Hardware Reference 3-33
External Port
The delay (in number of
SDCLK cycles) between consecutive refresh coun-
ter time-outs must be written to the RDIV field. A refresh counter time-out
triggers an auto-refresh command to the external SDRAM bank. Programs
should write the RDIV value to the SDRRC register before the SDRAM
power-up sequence is triggered. Change this value only when the SDC is
idle as indicated in the SDSTAT register.
To calculate the value to write to the SDRRC register, use the following
equation.
Where:
•f
SDCLK
= SDCLK frequency (SDRAM clock frequency)
•t
REF
= SDRAM refresh period
• NRA = Number of row addresses in SDRAM (refresh cycles to
refresh whole SDRAM)
•t
RAS
= Active to precharge time (SDTRAS bits in the SDRAM mem-
ory control register) in number of clock cycles
•t
RP
= RAS to precharge time (in the SDRAM memory control reg-
ister) in number of clock cycles
This equation calculates the number of clock cycles between required
refreshes and subtracts the required delay between bank activate com-
mands to the same bank (t
RC
= t
RAS
+ t
RP
). The t
RC
value is subtracted, so
that in the case where a refresh time-out occurs while an SDRAM cycle is
active, the SDRAM refresh rate specification is guaranteed to be met. The
result from the equation is always rounded down to an integer. Below is
an example of the calculation of
RDIV for a typical SDRAM in a system
with a 133 MHz SDRAM clock.
•f
SDCLK
= 133 MHz
RDIV
f
SDCLK
t
REF
×
NRA
------------------------------------
t
RAS
(– t
RP
)+
≤
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