ADSP-214xx SHARC Processor Hardware Reference 22-13
Power Management
General Notes on Power Savings
The following are some additional methods for reducing power.
• The lower the operation frequency, the lower the power consump-
tion. The core and peripherals should be operated at the lowest
frequency that meets the system’s requirements. Active power is
proportional to the processor’s core clock frequency.
• Reducing the case temperature lowers leakage power. Leakage
power increases exponentially to junction temperature.
• For core pauses programs should execute the IDLE instruction.
Note that an interrupt is required to release the processor from
IDLE.
• Don’t leave input pins floating. In some cases leakage draws cur-
rent in the region of milliamps. For more information, consult the
product specific data sheet. If an external resistor is problematic,
change the input to an output if possible (flag input).
• If a DAI/DPI pin is not being used, its pin enable (for example
DAI_PBENxx_I) and its input (DAI_PBxx_I) for its pin buffer should
be connected to low.
• Disable the S/PDIF receiver and its digital PLL from the S/PDIF
receiver. By default the S/PDIF receiver is enabled. If not required
set the DIR_RESET bit (=1) to disable the digital PLL which may
produce unwanted switching noise if enabled.
Programming Models
For SDRAM programming models, see “SDRAM Controller
(ADSP-2147x/ADSP-2148x)” on page 3-17.
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