Register Overview
13-6 ADSP-214xx SHARC Processor Hardware Reference
Register Overview
This section provides brief descriptions of the major registers. For com-
plete information see “Sony/Philips Digital Interface Registers” on
page A-199.
Transmit Control Register (DITCTL). The DITCTL register contains con-
trol parameters for the S/PDIF transmitter. The control parameters
include transmitter enable, mute information, over sampling clock divi-
sion ratio, SCDF mode select and enable, serial data input format select
and validity and channel status buffer selects.
Transmit Channel Status Registers (DITCHANAx/Bx). These registers
provide status bit information for transmitter subframe A and B in stand-
alone mode.
Transmit User Bit Registers (DITUSRBITAx/Bx). These registers pro-
vide user bit information for transmitter subframe A and B in standalone
mode.
Receive Control Register (DIRCTL). The
DIRCTL register contains con-
trol parameters for the S/PDIF receiver. The control parameters include
mute information, error controls, SCDF mode select and enable, and
S/PDIF PLL disable.
Outputs
DIR_CLK_O
DIR_TDMCLK_O
Group A, D
DIR_FS_O Group C, D
DIR_DAT_O Group B, D
DIR_LRCLK_FB_O
DIR_LRCLK_REF_O
Group D
Table 13-5. S/PDIF DAI/SRU Receiver Signal Connections (Cont’d)
Internal Node DAI Group SRU Register
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