Data Transfer Types
20-10 ADSP-214xx SHARC Processor Hardware Reference
latter clears the
DR bit. Reading the UARTRBR register clears both the
address-detect and the data-ready interrupts. In non-packed mode,
when the address-detect interrupt is generated, it means that the
data is ready in the RBR buffer while in packed mode, this is not
the case.
Data Transfer Types
The UART is capable of transferring data using both the core and DMA.
Not that data packing is available using both data transfer types. For more
information, see “Data Packing” on page 20-8.
Data Buffers
The UART contains a single data buffer register for transmission and
reception. These buffers are described in the following sections.
Transmit Holding Registers (UARTTHR)
A write to the UART transmit holding register (UARTTHR) initiates the
transmit operation. The data is moved to the internal transmit shift regis-
ter (UARTTSR) where it is shifted out at a baud rate equal to
PCLK/(16 × Divisor) with start, stop, and parity bits appended as required.
All data words begin with a 1-to-0 transition start bit. The transfer of data
from the UARTTHR register to the transmit shift register sets the transmit
holding register empty status flag (UARTTHRE) in the UART line status reg-
ister (
UARTLSR).
This 32-bit write only register uses only 18-bits. The other bits are filled
with zeros during writes. In no-pack mode (default), only the lower byte is
used—all other bits are zero filled. However in pack mode, both the high
and low bytes are used (Figure 20-3). The
TX9Dx bits are the ninth bit in
9-bit transmission mode. A write to the UART transmit holding register
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