ADSP-214xx SHARC Processor Hardware Reference A-101
Registers Reference
Control Base Address Register (MLB_CBCR)
The MLB_CBCR register, described in Table A-64, hold the base address of
the system memory buffers of all control channels in the device.
Isynchronous Base Address Register (MLB_IBCR)
The MLB_IBCR register, described in Table A-65, holds the base address of
the system memory buffers of all isynchronous channels in the device.
Logical Channel Registers
The MLB controller supports up to 31 logical channels. Therefore the
variable in the register names is valid for x = 0–30. This section lists all
different control and status registers related to the logical channels.
Table A-64. MLB_CBCR Register Bit Descriptions (RW)
Bit Name Description
4–0 CTBA Control transmit base address for DMA mode
15–5 Reserved
20–16 CRBA Control receive base address for DMA mode
31–21 Reserved
Table A-65. MLB_ABCR Register Bit Descriptions (RW)
Bit Name Description
4–0 ATBA Isynchronous transmit base address for DMA mode
15–5 Reserved
20–16 ARBA Isynchronous receive base address for DMA mode
31–21 Reserved
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