DDR2 DRAM Controller (ADSP-2146x)
3-76 ADSP-214xx SHARC Processor Hardware Reference
• 2 x 8-bit/page 1k words
• 4 x 4-bit/page 2k words
The DDR2’s page size is used to determine the system you select. All three
systems have the same external bank size, but different page sizes. Note
that larger page sizes, allow higher performance but larger page sizes
require more complex hardware layouts.
Even if connecting DDR2s in parallel, the DDR2C always consid-
ers the cluster as one external DDR2 bank because all address and
control lines feed the parallel parts.
Buffering Controller for Multiple DDR2s
If using multiples DDR2s or modules, the capacitive load will exceed the
controller’s output drive strength. In order to bypass this problem an
external register (SSTL18 class) can be used for decoupling by setting bit
24 in DDR2CTL0 register. This adds a cycle of data buffering to read and
write accesses.
Read Optimization
The best throughput numbers for reads are achievable only when the
DDR2OPT bit in the DDR2CTL0 register is set. To achieve better performance
for reads, predictive addresses need to be given to the DDR memory. The
predictive address given to the memory depends on the DDR2MODIFY bit
setting. If the
DDR2MODIFY value is 2 then the address + 2 is given
predictively on the DDR address pins. Programs have the option whether
to use read optimization or not.
It is advisable to use read optimization for core and DMA transfers, with a
constant modifier to achieve better performance. With multiple channels
running with ping-pong accesses, use arbitration freezing to get better
throughput.
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