SDRAM Controller (ADSP-2147x/ADSP-2148x)
3-24 ADSP-214xx SHARC Processor Hardware Reference
Auto-Refresh
The SDRAM internally increments the refresh address counter and causes
a CAS before RAS (CBR) refresh to occur internally for that address when
the auto-refresh command is given. The SDC generates an auto-refresh
command after the SDC refresh counter times out. The RDIV value in the
SDRAM refresh rate control register (SDRRC) must be set so that all
addresses are refreshed within the t
REF
period specified in the SDRAM
timing specifications.
Before executing the auto-refresh command, the SDC executes a pre-
charge all command to all external banks. The next activate command is
not given until the t
RFC
specification (t
RFC
= t
RAS
+ t
RP
) is met.
Auto-refresh commands are also issued by the SDC as part of the
power-up sequence and after exiting self-refresh mode.
No Operation/Command Inhibit
The no operation (NOP) command to the SDRAM has no effect on opera-
tions currently in progress. The command inhibit command is the same as
a NOP command; however, the SDRAM is not chip-selected. When the
SDC is actively accessing the SDRAM, but needs to insert additional
commands with no effect, the NOP command is given. When the SDC is
not accessing any SDRAM external banks, the command inhibit com-
mand is given.
Command Truth Table
Table 3-5 provides the bit states of the SDRAM for specific SDRAM
commands. Note that an X means do not care.
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