Analog Devices SHARC ADSP-214 Series - Page 153

ADSP-214xx SHARC Processor Hardware Reference 3-23
External Port
Figure 3-5 and Figure 3-6 show the SDRAM write and read timing of the
processors.
Figure 3-5. Write Timing Diagram
Figure 3-6. Read Timing Diagram
SDCLK
COMMAND
ACT
ACT
NOP
NOP
PREWR WR WR WR NOP
COL COL COL COL
AA AA
DDDD
ROW
A
ROW
A
t
RAS
t
RCD
t
RP
t
WR
t
RC
ADDR
BA[1:0]
DATA
SDCLK
COMMAND
ACT
ACT
NOP
NOP
PRERD RD NOP NOP NOP
COL COL
AA
DD
ROW
A
ROW
A
t
RAS
t
RCD
t
RP
CL
t
RC
ADDR
BA[1:0]
DATA
www.BDTIC.com/ADI