FFT Accelerator
6-18 ADSP-214xx SHARC Processor Hardware Reference
Peripheral Interrupt Control). Source bits
ACC0I and ACC1I are used to
connect FFT interrupts to the peripheral interrupt inputs of the core.
Table 6-2 povides an overview of FFT interrupts.
Interrupt Sources
One interrupt is shared by all the DMA interrupts and the other by MAC
status interrupts. Separate status registers are provided to further differen-
tiate the various sources.
Servicing DMA Interrupts
The DMA interrupt is shared by the input DMA and the output DMA.
The interrupts are generated at the end of every chain or at the end of an
entire DMA sequence, depending on the PCI value in the respective chain
pointer registers. When a DMA interrupt occurs, programs can find
whether the input DMA interrupt occurred or the output DMA interrupt
occurred by reading the DMA status register (FFT_DMASTAT). The DMA
interrupt status bits are sticky and are cleared when the DMA status regis-
ter is read.
Servicing MAC Status Interrupts
A MAC status interrupt is generated whenever a floating-point operation
results in an underflow or an overflow condition or when the operands of
a floating-point operand is a denormal number or NAN. When a MAC
Table 6-2. FFT Interrupt Overview
Interrupt
Sources
Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
FFT
(2 channels)
- Input DMA done
- Output DMA done
- MAC Status (NaN,
Denormal, Underflow,
overflow)
Internal transfer
completion
RTI instruction Need to route
ACCxI
(PICRx) to
any PxxI
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