ADSP-214xx SHARC Processor Hardware Reference A-255
Registers Reference
Slave Mode Control Register (TWISCTL)
The TWI slave mode control register (
TWISCTL) shown in Figure A-145
and described in Table A-138, controls the logic associated with slave
mode operation. Settings in this register do not affect master mode opera-
tion and should not be modified to control master mode functionality.
Figure A-145. TWISCTL Register
Table A-138. TWISCTL Register Bit Descriptions (RW)
Bit Name Description
0 TWISEN Slave Enable.
0 = The slave is not enabled. No attempt is made to identify a
valid address. If cleared during a valid transfer, clock stretching
ceases, the serial data line is released and the current byte is not
acknowledged.
1 = The slave is enabled. Enabling slave and master modes of
operation concurrently is allowed.
1TWISLEN Slave Address Length.
0 = Address is a 7-bit address
1 = Reserved. Setting this bit to 1 causes unpredictable behavior.
2TWIDVALSlave Transmit Data Valid.
0 = Data in the transmit FIFO is for master mode transmits and is
not allowed to be used during a slave transmit, and the transmit
FIFO is treated as if it is empty.
1 = Data in the transmit FIFO is available for a slave transmission.
TWISEN
TWIDVAL
TWINAK
TWIGCE
TWISLEN
Slave Enable
Slave Address Length
Slave Transmit Data Valid
Not Acknowledge
General Call Enable
09 837564 2114 12 11 101315
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