Data Transfer
3-90 ADSP-214xx SHARC Processor Hardware Reference
Instruction Packing
Any address produced by the sequencer which falls in external memory is
first translated into the physical address in external memory based on the
actual data bus width of external memory as shown in Figure 3-18.
The controller completes the required number of accesses from consecu-
tive locations for returning a 48-bit word instructions. For a 16-bit
SDRAM/DDR2 bus, it performs three accesses.
Only bank0 can be populated for external instruction fetch.
16-Bit Instruction Storage and Packing
In Table 3-19 the logical to physical translation is a multiplication by a
factor of 3 and N = 0x355554. Therefore, the 16-bit wide AMI memory
supports 3.3 million instructions.
In Table 3-19 P = 0xE00000. Therefore, the total number of external
memory instructions for a 16-bit wide SDRAM/DDR2 memory is 14
million.
Figure 3-18. Logical Versus Physical Addresses
EXTERNAL PORT
Sequencer
Logical
ADDR
Address
Translator
Instructions
48-bit
Physical
ADDR[23:0]
Instruction
Packing
16/48
8/48
External
Memory
SRAM
SDRAM
DDR2
Instruction fetch
(Packed 8/16 bit)
PM
Data
EP
Data
Bank0
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