ADSP-214xx SHARC Processor Hardware Reference 10-39
Serial Ports
Timing Control Bits
Several bits in the
SPCTLx register enable and configure packed mode.
• Internal Clock (ICLK)
• Internal Frame Sync (IFS)
• Sampling Edges Frame Sync/Data (CKRE)
• Selecting Channel Order (L_FIRST)
• Word Length (SLEN, 8–32 bits)
• Word Order (LSBF)
• Word Packing (PACK)
The following bits in the SPMCTLx register are used to configure timing
options in packed mode.
• Frame Delay (MFD)
• Number of multichannel channels (NCH)
Data Transfers
Serial port data can be transferred for use by the processor in two different
methods:
• Core-driven single word transfers
• DMA transfers between both internal and external memory
DMA transfers can be set up to transfer a configurable number of serial
words between the serial port buffers (
TXSPxA, TXSPxB, RXSPxA, and
RXSPxB) and internal memory automatically. Core-driven transfers use
SPORT interrupts to signal the processor core to perform single word
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