ADSP-2146x External Port Registers
A-24 ADSP-214xx SHARC Processor Hardware Reference
DDR2 Registers
The DDR2 controller contains seven memory-mapped control registers.
Note that when using the DDR2 registers:
• Programs may write to the DDR2 control registers as long as the
controller is not accessing memory devices. Otherwise, the control-
ler responds to any writes to its registers after it finishes any
ongoing memory accesses.
• The DDR2 control registers contain sensitive timing parameters
and settings for the DDR2. Carefully program these registers with
values that are in the operating range of the DDR2 used.
• Values in the reserved fields in these registers must be maintained
according to the DDR2 specification. Writing to reserved fields or
writing any reserved values in register bits cause the DDR2 to func-
tion erroneously.
• Programs must not change prefetch length fields of registers during
an ongoing transfer on data buses; otherwise unpredictable behav-
ior may occur.
Table A-10. AMISTAT Register Bit Descriptions (RO)
Bit Name Description
0 AMIMS External Bus Master.
1 = AMI controls the external pins
Since the AMI has dedicated pins AMIMS always reads 1.
1AMIS External Interface Status.
0 = AMI interface idle
1 = AMI access pending
15–4 Reserved
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