FFT Accelerator
6-14 ADSP-214xx SHARC Processor Hardware Reference
No Repeat Mode
If the
FFT_RPT bit = 0, after FFT_START = 1 the accelerator moves from the
idle state into the read state (input DMA). After the read completes, the
accelerator moves into the processing state then the write state to read the
results back into internal memory. The accelerator ends in the idle state.
For large FFTs (based on the VDIM, HDIM and NOVER256 bits) the accelerator
knows when the entire FFT processing has finished.
Repeat Mode
If the FFT_RPT bit = 1, after FFT_START = 1 the accelerator moves from the
idle state into the read state (input DMA). After the read completes, the
accelerator moves into the processing state then the write state to read the
results back into internal memory. The accelerator then moves automati-
cally back into the read state for the next FFT frame. In this state multiple
linked TCBs which were executed during the first iteration are re-used.
For large FFTs (based on the configuration of the VDIM, HDIM and
NOVER256 bits) the accelerator knows when the entire frame processing has
finished in order to re-load the new FFT frame parameters at the right
time.
Unpacked Data Mode
For small FFTs (FFT<=256), the unpacked data mode can be selected
independently for the input or output streams through the use of the
FFT_CPACKIN or FFT_CPACKOUT bits (FFTCTL2 register).
The FFT_CPACKIN/FFT_CPACKOUT settings are not applicable for N
3
512 points. The input is always expected to be in alternate real and
imaginary format and the output is always generated in the same
format.
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