ADSP-214xx SHARC Processor Hardware Reference 2-35
I/O Processor
During TCB chain loading, the I/O processor loads the DMA channel
parameter registers with values retrieved from internal memory.
When starting chain loading, note that the SPI port is an exception
to the above. To execute the first DMA in a chain for this periph-
eral, the DMA parameter registers also need to be explicitly
programmed. For more information, see “DMA Transfers” on
page 15-21.
The address in the chain pointer register points to the highest address of
the TCB (containing the index parameter). This means that if a program
declares an array to hold the TCB, the chain pointer register should point
to the last location of the array and not to the first TCB location.
The chain pointer register can be loaded at any time during the DMA
sequence. This allows a DMA channel to have chaining disabled (chain
pointer register address field = 0x0) until some event occurs that loads the
chain pointer register with a non zero value. Writing all zeros to the
address field of the chain pointer register also disables chaining.
TCB Chain Loading Priority
A TCB chain load request is prioritized like all DMA channels. Therefore,
the TCB chain loading request has the same priority level as the DMA
channel itself. The I/O processor latches a TCB loading request and holds
it until the load request has the highest priority. If multiple chaining
requests are present, the I/O processor services the TCB block for the
highest priority DMA channel first.
A channel that is in the process of chain loading cannot be inter-
rupted by any other request (TCB, DMA channel). The chain
loading sequence is atomic and the I/O bus is locked until all the
DMA parameter registers are loaded. For a list of DMA channels in
priority order, see Table 2-28.
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