ADSP-214xx SHARC Processor Hardware Reference A-81
Registers Reference
Channel Control Register (FIRCTL2)
The FIRCTL2 register, shown in Figure A-36 and described in Table A-48,
is used to configure the channel specific parameters such as filter TAP
length, window size, sample rate conversion, up/down sampling and ratio.
11 FIR_CCINTR Channel Complete Interrupt.
0 = Interrupt is generated only when all channels are done
(default)
1= Interrupt is generated after each channel is done
12 FIR_FXD Fixed-Point Accelerator Select.
0 = 32-bit IEEE floating-point
1 = 32-bit fixed point
13 FIR_TC Two’s-Complement Format Input Select For Fixed-Point
Mode.
0 = Unsigned integer
1 = Signed intiger
16–14 FIR_RND Rounding Mode Select For Floating-Point Mode.
000 = IEEE round to nearest (even)
001 = IEEE round to zero
010 = IEEE round to +ve infinity
011 = IEEE round to -ve infinity
100 = Round to nearest Up
101 = Round away from zero
110 = Reserved
111 = Reserved
31–17 Reserved
Table A-47. FIRCTL1 Register Bit Descriptions (RW) (Cont’d)
Bits Name Description
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