Peripheral Registers
A-82 ADSP-214xx SHARC Processor Hardware Reference
Figure A-36. FIRCTL2 Register
Table A-48. FIRCTL2 Register Bit Descriptions (RW)
Bits Name Description
11–0 TAPLEN Tap Leng t h . Programmable between 0–4095
Tap Length = TAPLEN + 1
13–12 Reserved
23–14 WINDOW Window Size. Programmable between 0–1023
Window Size = WINDOW+ 1. A window size of 1 corre-
sponds to sample based operation and the maximum win-
dow size is 1024.
24 Reserved
27–25 FIR_RATIO UP/DOWN Sampling Ratio.
Sampling Ratio = RATIO + 1
28 Reserved
29 FIR_SRCEN Sample Rate Conversion Enable.
0 = Disabled
1 = Enabled
30 FIR_UPSAMP Up Sampling Enable.
0 = Down Sampling
1 = Up sampling
31 Reserved
TAPLEN (11–0)
WINDOW (23–14)
Window Size
Tap Length
FIR_UPSAMP
Up Sampling Enable
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
WINDOW (23–14)
Window Size
FIR_SRCEN
Sample Rate Conversion
Enable
FIR_RATIO
Up/Down Sampling Ratio
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