ADSP-214xx SHARC Processor Hardware Reference A-43
Registers Reference
DDR2 Pad Control Register 0 (DDR2PADCTL0)
The
DDR2PADCTL0 register shown in Figure A-18 and described in
Table A-23 includes the programmable parameters associated with the
DDR2 DATA, DQS and DDR2CLK pads.
Figure A-18. DDR2PADCTL0 Register
Table A-23. DDR2PADCTL0 Register Bit Descriptions (RW)
Bit Name Description
8–0 Reserved
9DATA_PWDData Pad Receiver Power Down.
0 = Normal mode
1 = Power-down mode
18–10 Reserved
19 DQS_PWD DQS Pad Receiver Power Down.
0 = Normal mode
1 = Power-down mode
28–20 Reserved
29 DDR2CLK_PWD Clock Pad Receiver Power Down.
0 = Normal mode
1 = Power-down mode
31–30 Reserved
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
DATA_PWD
Receiver Power Down
DQS_PWD
Receiver Power Down
DDR2CLK_PWD
Receiver Power Down
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