Operating Modes
14-16 ADSP-214xx SHARC Processor Hardware Reference
• SRU is the input source. If the input clock and trigger signal are
synchronous, the delay is exactly 3 input clock periods. If asyn-
chronous, it varies between 2.5 to 3.5 input clock periods
depending on the phase difference between the input clock and
trigger signal.
Audio System Example
Figure 14-6 shows an example of the internal interconnections between
the SPDIF receiver, ASRC, and the PCGs. The interconnections are made
by programming the signal routing unit.
It shows how to set up two precision clock generators using the S/PDIF
receiver and an asynchronous sample rate converter (ASRC) to interface to
an external audio DAC. The PCG is configured to provide a fixed
ASRC/DAC output sample rate of 65.098 kHz. The input to the S/PDIF
receiver is typically 44.1 kHz if supplied by a CD player, but can also be
from other source at any nominal sample rate from about 22 kHz to 192
kHz.
Similarly, the phase shift for frame syncs B, C, and D is specified in the
corresponding PCG_CTLxO and PCG_CTLx1 registers.
Three synchronous clocks are required in audio systems
1. Frame sync (
FS)
2. Serial bit clock (64 x FS)
3. Master DAC clock (256 x FS)
Since each PCG has only two outputs, this example requires two PCGs.
Furthermore, because the digital audio interface requires a fixed-phase
relation between SCLK and FS, these two outputs should come from one
PCG (PCG A) while the master clock comes from the 2nd (PCG B).
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