Asynchronous Memory Interface
3-12 ADSP-214xx SHARC Processor Hardware Reference
The external interface follows standard asynchronous SRAM access proto-
col. The programmable wait states, hold cycle and idle cycles are provided
to interface memories of different access times. To extend access the
ACK
signal can be pulled low by the external device as an alternative to using
wait states.
Asynchronous Reads
Figure 3-3 shows an asynchronous read bus cycle. Asynchronous read bus
cycles proceed as follows.
1. At the start of the setup period, MSx and AMI_RD assert. The address
bus becomes valid.
2. At the beginning of the read access period and after the 3rd cycles,
AMI_RD deasserts.
3. At the beginning of the hold period, read data is sampled on the
rising edge of the SDCLK clock.
4. At the end of the hold period, some IDLE cycles happened in the
case the read is followed by a write. Also, MSx deasserts unless the
next cycle is to the same memory bank.
Asynchronous Writes
Figure 3-4 shows an asynchronous write bus cycle. Asynchronous write
bus cycles proceed as follows.
1. At the start of the setup period,
MSx, the address bus, data buses,
become valid.
2. At the beginning of the write access period,
WR asserts.
3. At the beginning of the hold period,
WR deasserts.
4. One hold cycle is introduced before next access can happen. Also,
MSx deasserts unless the next cycle is to the same memory bank.
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