Data Transfer
8-8 ADSP-214xx SHARC Processor Hardware Reference
Big-Endian and Little-Endian Mode
The byte order in which data is transferred between local channel buffers
and internal memory is determined by enabling either big-endian or lit-
tle-endian mode. Both data transfer methods, DMA and I/O mode
support big-endian and little-endian system memory data formats. This
option is selected using the MLE bit in the MLB_DCCR register.
Data Transfer
Two modes of operation are supported for transferring channel data
between the MLB and internal memory. DMA allows the multi-channel
DMA engine to manage data transfers without core intervention. Core
driven mode (I/O mode) allows software to manage the transfer of data
between MLB and internal memory.
All hardware channels must use the same data transfer method. Mixed
mode operation where hardware channels operate in both I/O mode and
DMA mode is not supported.
Core Driven Data Transfer
Core driven mode is an interrupt driven data transfer method between
hardware channels and internal memory. When the MLB is configured in
I/O mode, the MLB_CCBCRx and MLB_CNBCRx registers are used as the receive
data buffer and transmit data buffer respectively. Transmit and receive ser-
vice request interrupts are generated when data is to be transferred from/to
internal memory to/from MLB local channel buffer.
I/O Local Channel Buffering
As shown in Figure 8-2, once a quadlet is received on the MLB bus, it is
transferred to the corresponding local channel buffer. The data transfer
takes place from this local channel buffer to internal memory. The size of
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