ADSP-214xx SHARC Processor Hardware Reference 16-21
Peripheral Timers
Programming Model
The section describes which sequences of software steps are required to get
the peripheral working successfully.
To enable an individual timer, set the timer’s TIMxEN bit in the TMSTAT reg-
ister. To disable an individual timer, set the timer’s TIMxDIS bit in the
TMSTAT register. To enable both timers in parallel, set all the TIMxEN bits in
the TMSTAT register.
Before enabling a timer, always program the corresponding timer’s config-
uration (TMxCTL) register. This register defines the timer’s operating mode,
the polarity of the TIMERx signal, and the timer’s interrupt behavior. Do
not alter the operating mode while the timer is running. For more infor-
mation, see “Timer Configuration Registers (TMxCTL)” on page A-270.
PWM Out Mode
Use the following procedure to configure and run the timer in PWM out
mode.
1. Reset the TIMEN bit and set the configuration mode to 01 to select
PWM_OUT operation. This configures the TIMERx_O pin as an
output pin with its polarity determined by the PULSE bit.
• The timer outputs a positive active pulse width at the
TIMERx_O pin.
• The timer outputs a negative active pulse width at the
TIMERx_O pin.
2. Initialize the period and width register values. Insure that the
period value is greater than the width value.
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