Effect Latency
3-120 ADSP-214xx SHARC Processor Hardware Reference
Table 3-33 illustrates the performance of code execution depending on
different access types.
When executing from external asynchronous memory, instruction
throughput depends on the settings of asynchronous memory such as the
number of wait states, the ratio of core to peripheral clock and other
settings. For details, please refer to the external port global control register
(
EPCTL), the AMICTLx register, and the SDCTL0 register in “ADSP-2147x,
ADSP-2148x External Port Registers” on page A-45.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific). After the
AMI/SDRAM/DDR2 registers are configured the effect latency is 1.5
PCLK cycles minimum and 2 PCLK cycles maximum.
After the external port register is configured the effect latency is 4 PCLK
cycles. This is the valid for the worst case of core to SDRAM/DDR2 clock
ratio of 1:4
Table 3-33. Core Throughput
Access Data
Width
Page Throughput per
SDCLK (CL = 2)
Throughput per
SDCLK (CL = 3)
Sequential uninter-
rupted reads
16 Same 2 instructions per 6
cycles*
2 instructions per 6
cycles*
Non sequential uninter-
rupted reads
16 Same 1 instructions per 9
cycles
1 instructions per 10
cycles
* In this case SDC has to fetch 3 data (16-bit) for each instruction.
First 48-bit instruction of a sequential read will take 8 cycles for CL = 2 and 9 cycles for
CL = 3, thereafter it is two instructions per 6 cycles.
The instruction available cycles will look like - 8, 10, 14, 16, 20, 22, 26, 28 … (CL = 2)
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