Interrupts
12-16 ADSP-214xx SHARC Processor Hardware Reference
A 12-bit counter, clocked by
SRCx_FS_IP_I, is used to control the mute
attenuation. Therefore, the time it takes from the assertion of MUTE_IN to
–144 dB, full mute attenuation is 4096 FS cycles.
Likewise, the time it takes to reach 0 dB mute attenuation from the deas-
sertion of MUTE_IN is 4096 FS cycles.
Hard Mute
When the SRCx_HARD_MUTE bit in the SRCCTL register is set, the SRC imme-
diately mutes the input data to the SRC FIFO to zero, (–144 dB)
attenuation.
Auto Mute
When the SRCx_AUTO_MUTE bit in the SRCCTLx register is set, the SRC com-
municates with the S/PDIF receiver peripheral to determine when the
input should mute. Each SRC is connected to the S/PDIF receiver to read
the DIR_NOAUDIO bits. When the DIR_NOAUDIO bit is set (=1), the SRC
immediately mutes the input data to the SRC FIFO to zero, (–144 dB)
attenuation.
This mode is useful for automatic detection of non-PCM audio data
received from the S/PDIF receiver.
Interrupts
The SRC mute-out signal can be used to generate interrupts on their ris-
ing edge, falling edge, or both, depending on how the DAI interrupt mask
registers (
DAI_IMASK_RE/FE) are programmed. This allows the generation
of
DAIHI/DAILI interrupts either entering mute, exiting muting or both.
The SRCx_MUTE_OUT interrupt is generated only once when the SRC is
locked (after 4096 FS input samples) and after changes to the sample
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