External Port Throughput
3-116 ADSP-214xx SHARC Processor Hardware Reference
completion or access completion. The following also effect interrupt
generation.
• For standard chained DMA, if the
PCI bit is cleared (= 0), the
DMA complete interrupt is generated only after the entire chained
DMA access is complete. If the PCI bit is set (= 1), then a DMA
interrupt is generated for each TCB.
• For the delay line DMA, the DMA complete interrupt is generated
when both the write access and the delay line reads are completed.
In a chained delay line DMA, the PCI bit determines if each delay
line TCB generates an interrupt or not.
• With scatter/gather DMA, the DMA complete interrupt is gener-
ated only after all tap list reads/writes are complete. As in the delay
line DMA, the PCI bit setting determines if each tap list TCB gen-
erates an interrupt in a chained access.
If DMA is disabled in the middle of data transfers, the DMA inter-
rupts should not be used.
External Port Throughput
The following sections provide information on the throughput of the
external port interfaces (AMI, SDRAM).
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