ADSP-214xx SHARC Processor Hardware Reference 7-25
Pulse Width Modulation
The PWM sync enable feature allows programs to enable the
PWN_SYNC_ENx bits to independently start the main counter without
enabling the corresponding PWM module using the PWM_ENx bits. To syn-
chronize different groups, enable the corresponding group’s PWM_ENx bit at
the same time. In order to stop the counter both the PWM_DISx and
PWM_SYNC_DISx bits should be set in this register.
Interrupts
The following sections provide information on the PWM and interrupt
generation. Table 7-5 provides an overview of PWM interrupts.
Typically the PWM interrupt is used to periodically execute an interrupt
service routine (ISR) to update the two PWM channel duties according to
a control algorithm based on expected system operation. The PWM inter-
rupt can trigger the ADC to sample data for use during the ISR. During
processor boot the PWM is initialized and program flow enters a wait
loop. When a PWM interrupt occurs, the ADC samples data, the data is
algorithmically interpreted, and new PWM channel duties are calculated
and written to the PWM. More sophisticated implementations include
different startup, runtime, and shutdown algorithms to determine PWM
channel duties based on expected behavior and further features.
During initialization, the PWMTM register is written to define the PWM
period and the
PWMCHx registers are written to define the initial channel
pulse widths. The PWM interrupt is assigned to one of the core’s User
Table 7-5. PWM Interrupt Overview
Interrupt Source Interrupt
Condition
Interrupt
Completion
Interrupt Acknowledge Default IVT
PWM (Edge/center
aligned, single/double
update, 4 channels)
Period start W1C (Write 1-to-clear)
PWMGSTAT + RTI
instruction
Need to route
PWMI (PICRx)
to any PxxI
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