Interrupts
7-26 ADSP-214xx SHARC Processor Hardware Reference
interrupts and is unmasked in the core. The
PWMSEG and PWMCHx registers
are also written, depending on the system configuration and modes. Dur-
ing the PWM interrupt driven control loop, only the PWMCHx duty values
are typically updated. The PWMSEG register may also be updated for other
system implementations requiring output crossover.
For interrupt execution, the specific PWM_IRQEN bit in the corresponding
PWMCTLx register must be set including the IMASK or LIRPTL registers based
on the programmable interrupt to be used.
Whenever a period starts, the PWM interrupt is generated. The interrupt
latch bit is set 1 PCLK cycle after the PWM counter resumes. Since all four
PWM units share the same interrupt vector, the interrupt service routine
should read the PWMGSTAT register in order to determine the source of the
interrupt. Next, the ISR needs to clear the status bits of the PWMGSTAT reg-
ister by explicitly writing 1 into the status bit (W1C) as shown in
Listing 7-1.
Listing 7-1. Writing 1 Into the Status Bit
GPWM_ISR:
ustat2=dm(PWMGSTAT); /* read global status reg */
bit tst ustat2 PWM_STAT2; /* test PWM2 status */
if tf jump PWM2_ISR; /* jump to PWM2 routine */
instruction;
instruction;
PWM2_ISR:
r1=PWM_STAT2;
dm(PWMGSTAT)=r1; /* W1C to clear PWM2 interrupt */
r10=dm(PWMCTL2); /* dummy read for write latency */
instruction;
rti;
To Next Page
Loading...
Need help?
General
