ADSP-214xx SHARC Processor Hardware Reference 10-55
Serial Ports
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
SPORT Effect Latency
After a write to a SPORT control register, control and mode bit changes
take effect in the second serial clock cycle (SCLK).
The SPORT is ready to start transmitting or receiving three serial clock
cycles after they are enabled in the SPCTLx control register. No serial clocks
are lost from this point on. This delay does also apply in slave mode
(external clock/frame sync) for synchronization.
Multichannel and packed operation is activated 3 serial clock cycles (SCLK)
after the MCEA or MCEB bits are set. Internally-generated frame sync signals
activate 4 serial clock cycles after the MCEA or MCEB bits are set.
Programming Model
The section describes some programming procedures that are used to
enable and operate the SPORTs.
Setting Up and Starting DMA Master Mode
To set up and initiate a master DMA operation, use the following
procedure.
1. Clear the SPORT control register (
SPCTLx).
2. Write to the appropriate
DIVx register, setting the master clock and
frame sync ratios.
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