Functional Description
2-24 ADSP-214xx SHARC Processor Hardware Reference
A. When the transfer is completed as per the value in the count register,
the DMA restarts with the memory location indexed by B. The DMA
restarts with index A after the transfer to memory with index B is com-
pleted as per the count value. This repeats until the DMA is stopped by
resetting the DMA enable bit.
Circular Buffering DMA (FFT, FIR, IIR, External Port). This mode
resembles the chained DMA mode, however two additional registers (base
and length) are used. This mode performs DMA within the circular buf-
fer, which is useful for filter implementation since core interaction is
limited, conserving bandwidth.
DMA Direction
The IOP supports DMA in three directions. These are described in the
following sections.
Internal to External Memory
DMA transfers between internal memory and external memory devices use
the processor’s external port. For these types of transfers, the application
code provides the DMA controller with the internal memory buffer size,
address, and address modifier, as well as the external memory buffer size,
address, address modifier, and the direction of transfer. After setup, the
DMA transfers begin when the program enables the channel and contin-
ues until the I/O processor transfers the entire buffer to processor
memory. Table 2-28 on page 2-36 shows the parameter registers for each
DMA channel.
Peripheral to Internal Memory
Similarly, DMA transfers between internal memory and serial, IDP, or
SPI ports have DMA parameters. When the I/O processor performs DMA
between internal memory and one of these ports, the program sets up the
parameters, and the I/O uses the port instead of the external bus.
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