ADSP-214xx SHARC Processor Hardware Reference 3-75
External Port
•t
RFC
(row refresh cycle). Required delay time to refresh a single
row. This parameter is fixed to t
RFC
=t
RC
cycles.
•t
XSNR
(exit self-refresh with non-read). Required delay to exit the
self-refresh mode with a non read command. This parameter is
fixed to t
XSNR
= t
RFC
+ 4 cycles.
•t
XSRD
(exit self-refresh with read). Required delay to exit the
self-refresh mode with a read command. This parameter is fixed to
t
XSRD
= 200 cycles.
The DDR2 controller controls the following ODT related timing parame-
ters, no user programming is required.
•t
ANPD
(ODT to power-down entry latency)
•t
AXPD
(ODT to power down exit latency)
•t
AOND
(ODT turn on delay)
•t
AOFD
(ODT turn off delay)
•t
AON
(ODT turn on time)
•t
AOF
(ODT turn off time)
Operating Modes
The following sections provide on the operating modes of the DDR2
interface.
Parallel Connection of DDR2s
To specify a DDR2 system, multiple possibilities are given based on the
different memory sizes. For a 16-bit I/O capability, the following memory
sizes can configured.
• 1 x 16-bit/page 512 words
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