Analog Devices SHARC ADSP-214 Series

SDRAM Controller (ADSP-2147x/ADSP-2148x)
3-40 ADSP-214xx SHARC Processor Hardware Reference
SDRAM Read Optimization
To achieve better performance, read addresses can be provided in a predic-
tive manner to the SDRAM memory. This is done by setting (=1) the
SDROPT bit (bit 16) and correctly configuring the SDMODIFY bits
Figure 3-10. Uniprocessor System With Multiple Buffered SDRAM
Devices
DATA[3:0]
DQM
S
MS3
RAS
CAS
SDWE
SDCLK
SDCKE
C
O
N
T
R
O
L
A
D
D
R
E
S
S
REGISTERED
BUFFERS
I0
I5
I4
I2
I1
O0A
O4A
O3A
O2A
O1A
OXA[12
- 0]
RAS
CAS
WE
CLK
CKE
SDRAM #1
32M x 4 x 4
A[14
- 0]
CS
DATA[3:0]
DQ
DQ
ADDR [15]
CTRL [6]
21
21
SDRAM BANK 1
ADDR & CTRL
DATA[3:0]
SDA10
A17
A18
DQM
DQM
DQM
SDDQM
SDRAM BANK 2
ADDR & CTRL
A[12 - 11]
A[9
- 0]
DATA [3
- 0]
DATA [3
- 0]
DATA [7
- 4]
DATA [11
- 8]
DATA [15
- 12]
DATA [15
- 0]
SDRAM #2
32M x 4 x 4
SDRAM #3
32M x 4 x 4
SDRAM #4
32M x 4 x 4
IXA[12
- 0]
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