ADSP-214xx SHARC Processor Hardware Reference 22-15
Power Management
Multiplier and Post Divider Programming Model
There are two allowable procedures to program the VCO. The first
method is shown in Listing 22-3.
1. Set the PLL multiplier and divisor value and enable the divisor by
setting the
DIVEN bit.
2. After one core clock cycle, place the PLL in bypass mode by setting
(= 1) the
PLLBP bit. Clear the DIVEN bit while placing the PLL into
bypass mode.
3. Wait in bypass mode until the PLL locks (4096 CLKIN cycles).
4. Take the PLL out of bypass mode by clearing (= 0) the bypass bit.
Clear the DIVEN bit while taking the PLL out of bypass mode.
5. Wait 15 core cycles before next activity.
The second method is:
1. Set the PLL multiplier and divisor values and place the PLL in
bypass mode by setting the PLLBP bit. The second method is shown
in Listing 22-4.
2. Wait in the bypass mode until the PLL locks (4096 CLKIN cycles).
3. Take the PLL out of bypass mode by clearing the bypass bit.
4. Wait for one core clock cycle.
5. Enable the divisor by setting the
DIVEN bit.
6. Wait 15 core cycles before next activity.
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