S/PDIF Transmitter
13-12 ADSP-214xx SHARC Processor Hardware Reference
To allow user bit updates, write a 0x1 to the
DIT_USRUPD register that is
used for further processing. If the DIT_AUTO bit in the DITCTL register is
set:
• At every 192nd Frame end, if DITUSRUPD = 1, then the user status
bits are taken from user bits buffers and transmitted. Simultane-
ously, the DIT_USRUPD register is cleared automatically by hardware.
• At every 192nd Frame end, if DITUSRUPD = 0 then the user status
bits are updated as zeros and transmitted. The DIT_USRUPD register
remains low.
For the first block of transfer, write a one (1) to the DITUSRUPD reg-
ister and then enable the S/PDIF transmitter.
In general, for the next block, programs can update user bits buffers at any
time during the transfer of the current block (1 block = 192 frames).
There are internal buffers to store the user status bits of the current block
of transfer. In other words, at the beginning of every new block, the user
status bit (DIT_USRPEND in the DITCTL register) from user bits buffers are
copied to internal buffers and transmitted in each frame during the
transfer.
Note that since a frame contains 192 bits/8 = 24 bytes, six status/user reg-
isters are required to store each four bytes.
Data Output Mode
Two output data formats are supported by the transmitter; two channel
mode and single-channel double-frequency (SCDF) mode. The output for-
mat is determined by the transmitter control register (
DITCTL).
In two channel mode, the left channel (channel A) is transmitted when the
DIT_FS_I is high and the right channel (channel B) is transmitted when
the DIT_FS_I is low.
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