Pin Multiplexing
23-28 ADSP-214xx SHARC Processor Hardware Reference
During the boot process, word packing (for example 8 to 32-bit) is per-
formed over the SPI. In other words, the kernel is not loaded directly with
256 x 48-bit words, instead it is loaded with 384 x 32-bit ‘packed words’
(2-column access). The same physical memory for instruction boot is
loaded via DMA in normal word (NW) 2 column. However, after booting
the same physical memory region is fetched by the sequencer in NW
3-column. For example the loader kernel itself has a NW 2 columns count
of 256 x 3/2 = 384 words but the kernel is executed with 256 instruction
fetches.
Note that the interrupt vector table addresses are defined as:
IVT_Start_Addr = 0x8C000 and IVT_End_Addr = 0x8C0FF.
Pin Multiplexing
The SHARC processors provide extensive functionality using a low pin
count (reducing system cost). They do this through extensive use of pin
multiplexing. The following sections provide information on this feature.
Although the processors have the efficient and flexible DAI and DPI rout-
ing options, there are also I/O pins which are shared by some peripherals.
The following sections discusses these options.
On the ADSP-2146x processors the AMI and DDR2 interfaces are
completely independent (not multiplexed). Only the AMI control-
ler address/memory selects and data pins are shared and therefore
all pins discussed in this section refer to the AMI controller.
Core FLAG Pins Multiplexing
This module also includes the multiplexers of the FLAG0-3 pins shown in
Figure 23-10. The
FLAG0-2 pins can act as core FLAGS0-2 or IRQ0-2, or a
memory select
MS2 (FLAG2 pin) and the FLAG3 pin can act as a core FLAG3 or
the TMREXP signal of the core timer or as a memory select MS3.
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