Peripheral Registers
A-114 ADSP-214xx SHARC Processor Hardware Reference
Watchdog Timer Registers
The following sections provide bit descriptions for the registers associated
with the watchdog timer.
Control (WDTCTL)
The watchdog control register (WDTCTL), is a 32-bit system mem-
ory-mapped register used to configure the watchdog timer.
WDTCTL is
protected against accidental writes from the processor core by the watch-
dog unlock register (
WDTUNLOCK). Attempts by the core to write to WDTCTL
without an unlock command causes the WDT to expire, and reset the sys-
tem. This condition is captured in the watchdog exception field (WDERR).
Writes made by software to this register keep it enabled. Only an External
hardware reset can disable WDTCTL.
Status (WDTSTATUS)
The WDTSTATUS register, shown in Figure A-51 and described in
Table A-72, contains the watchdog timer status information. This register
is not cleared by the WDT generated reset.
Figure A-51. WDTSTATUS Register
WDRO
Slave Transfer Direction
09 837564 2114 12 11 101315
WDERR
Error
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